![]() ![]() For example, Cray's “Adaptive Supercomputing” strategy is to apply a variety of processors (vector, scalar, multithreading) that excel at different types of workloads. In HPC, the conventional answer to heterogeneity is to use different types of processors. A polymorphic processor could be applied to any application that consisted of high performance heterogeneous workloads, embedded or otherwise. The DoD would love to find a solution that can approach the performance of a specialized processor, yet retain the ability to be used for many different types of applications. The specialized and general-purpose processors become idle or stressed as the workload throttles up and down, reducing system efficiency. In this type of environment, the workload is often volatile. Currently the Department of Defense (DoD) builds numerous mobile computing systems that incorporate a vast range of custom ASICs, often alongside general-purpose commodity processors. It is this polymorphic behavior that is of particular interest to DARPA. More than that, a TRIPS processor is able to change its execution behavior based on the application profile, so that workloads requiring different levels of parallelism (instruction, data, and thread) may all be accommodated efficiently. The rationale is that this frees the hardware from having to reconstruct these dependencies at runtime. ![]() ![]() It does this via its EDGE ISA, which allows a compiler to specify the data dependencies during code generation. In contrast, TRIPS uses heavy-duty instruction-level concurrency to achieve high levels of performance. Today, the commercial solution to high performance is to add more cores to general purpose processors (i.e., x86, Power, UltraSPARC) or use special processing units for acceleration (i.e., GPUs, the Cell processor, ClearSpeed boards). On Monday, the team, led by UT professors Doug Burger, Steve Keckler and Kathryn McKinley, unveiled the first TRIPS prototype. With $20 million of funding, primarily from DARPA, the UT research team developed the Tera-op Reliable Intelligently adaptive Processing Systems (TRIPS) architecture. In the midst of the multicore frenzy that has enveloped processor design over the past several years, researchers at the University of Texas (UT) have been methodically working on a very different kind of chip architecture. Since 1987 - Covering the Fastest Computers in the World and the People Who Run Them ![]()
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